The present invention generally relates to the field of semiconductors, and more particularly relates to a method of fabricating vertical transistor structures on semiconductor chips.
Fin field-effect transistor (fin FET) devices include a transistor architecture that uses raised source-to-drain channel regions, referred to as fins. A fin FET device can be built on a semiconductor substrate, where a semiconductor material, such as silicon, is patterned into a fin-like shape and functions as the channel of the transistor. Known fin FET devices include fins with source/drain regions on lateral sides of the fins, so that current flows in a horizontal direction (e.g., parallel to the semiconductor substrate) between source/drain regions at opposite ends of the fins in the horizontal direction.
More recently, vertical fin field-effect transistors have been explored. This vertical arrangement of a transistor device can help increase the number of transistors that can fit on a chip without having to substantially increase the overall chip size. Vertical transport architecture FET devices include source/drain layers at ends of vertically oriented fins, i.e., on top and bottom sides of the vertical fins, so that current flows through the fins in a vertical direction (e.g., perpendicular to the semiconductor substrate) between a bottom source/drain layer and a top source/drain layer.
Different transistors on the same chip can be used for different performance and power applications. The gate length of a fin FET can be varied to vary the performance and the power consumption in the transistor. The shorter gate length transistors have higher performance (e.g., higher speed) and higher power consumption, while the longer gate length transistors have lower performance (e.g., lower speed) and lower power consumption. Circuit designs can trade-off power and performance parameters by varying the gate length of the transistors.
It is difficult to get different gate lengths for different vertical fin FET devices on the same chip because the gate length in a vertical fin FET device is not defined by lithography.